1. Field of the Invention
The invention relates in general to DC—DC converters, and more particularly to DC—DC converters that are capable of outputting three times amplified, and two times amplified and inverted voltages.
2. Description of the Related Art
DC—DC converter is a circuit device that receives an input DC voltage and produces a DC output voltage. DC—DC converters have been used to amplify DC voltages, or to invert input DC voltages and output them as negative voltages. Due to their ability to receive low input voltages and consume low power, DC—DC converters have been widely used in all types of electronic products.
Low temperature poly-Si LCDs (liquid crystal display) are equipped with the technology to integrate circuits onto the glass substrate. Thus, integrating the DC—DC converter onto the LCD panel can result in many advantages including the reduction of the surrounding area, the ability to have low voltage supply and a single DC voltage source input, the reduction in production costs, and the ability to apply in mobile electronic products.
FIG. 1A is a circuit diagram of the traditional DC—DC converter. DC—DC converter 100, applying the theory of charge pump, uses clock signals {overscore (φ1)}, φ2, φ1 and φ2 to control transistors SW1, SW2, SW3 and SW4, and converts input voltage VDD to output voltage Vo1 of 2VDD. Then DC—DC converter uses clock signals φ2, {overscore (φ2)}, {overscore (φ2)} and {overscore (φ2)} to control transistors SW5, SW6, SW7 and SW8, and converts the value of output voltage Vo1 to an output voltage Vo2 of 3VDD, and also uses clock signals φ2, φ2, {overscore (φ1)}, and φ1 to control transistors SW9, SW10, SW11 and SW12, and converts output voltage Vo1 to output voltage Vo3 of −2VDD.
As shown in FIG. 1B, at time T1, the voltage level of clock signal φ1 is at VDD, the voltage level of clock signal φ2 is at 3VDD, and the voltage level of clock signal {overscore (φ1)} is at −2VDD. At this time, transistor SW1 and SW4 turn on, but transistor SW2 and SW3 remain off, making the voltage across capacitor C1 to equal VDD. At time T2, clock signal φ1 is at −2VDD, clock signal φ2 is at 0V, clock signal {overscore (φ1)} is at VDD, and clock signal {overscore (φ2)} is at 3VDD. At this time, transistors SW1 and SW4 are turned off, and transistor SW2 and SW3 are turned on, causing output voltage Vo1 to become 2VDD. In addition, at time T2, transistors SW5 and SW7 are turned on, and SW6 and SW8 are turned off, causing the voltage across C2 to be VDD. And transistors SW10 and SW11 are turned on, and transistors SW9 and SW12 remain off, causing the voltage across C3 to be 2VDD.
At time T3, clock signal φ1 is at signal level VDD, clock signal φ2 is at 3VDD, clock signal {overscore (φ1)} is at −2VDD, and clock signal {overscore (φ2)} is at 0V. At this time, transistors SW5 and SW7 are turned off, and transistors SW6 and SW8 are turned on, causing output voltage Vo2 to become 3VDD. And transistors SW10 and SW11 are turned off, and transistors SW9 and SW12 are turned on, causing output voltage Vo3 become −2VDD.
However, the described DC—DC converter 100 must use additional shift register 110 and 120 to convert clock signal CLK individually into the described clock signals φ1, {overscore (φ1)}, φ2 and {overscore (φ2)}, as shown on FIG. 1C. Only then the DC—DC converter 100 can output the expected two times amplified, three times amplified, and two times amplified and inverted output voltages. However, the positive bias VDD and negative bias −2VDD of level shifter 110, and the positive bias 3VDD of level shifter 120 are provided by the DC—DC converter 100, thus, this structure will not only increase the loading of DC—DC converter 100, but also aggravate the time required for DC—DC converter 100 to output stabilized voltage.
FIG. 2 is a circuit diagram of the DC—DC converter disclosed by U.S. Pat. No. 6,509,894. DC—DC converter 210 or 220 uses the clock signal HCK of the shift register (not shown on the figure) on the panel of low temperature poly-Si LCD as the clock signal, and uses inverter 211 and 212 or inverter 221 and 222 to output clock signals φ11 and φ12 or clock signals φ21 and φ22. The clock signals are used to charge and discharge the capacitors C11 and C12 or C21 and C22 to control transistors T11, T12 and T13 or transistors T21, T22, and T23, and cause DC—DC converter 210 or 220 to be able to amplify the DC input voltage to produce twice amplified and inverted output voltages.
However, the high voltage levels of clock signal HCK of the shift register (not shown on the figure), located on the panel of the low temperature poly-Si LCD, are mostly at 3.3V. In order to produce a positive output voltage 2VDD of 9˜10V, and a negative output voltage −VDD of −6.5V˜−5V, the DC input voltage VDD and the positive bias voltage VDD of inverter 211, 212, 221 and 222 must be equal to 5V. Thus, the DC—DC converter of the LCD as disclosed by U.S. Pat. No. 6,509,894 must use an additional 5V DC voltage source and thereby increases the production cost of the system and the power consumption.